#ifndef F28P65X_AES_H
#define F28P65X_AES_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// AES Individual Register Bit Definitions:

struct AES_CTRL_BITS
{                            // bits description
    Uint32 OUTPUT_READY : 1; // 0 Output Ready Status
    Uint32 INPUT_READY  : 1; // 1 Input Ready Status
    Uint32 DIRECTION    : 1; // 2 Encryption/Decryption Selection
    Uint32 KEY_SIZE     : 2; // 4:3 Key Size
    Uint32 MODE         : 1; // 5 ECB/CBC Mode
    Uint32 CTR          : 1; // 6 Counter Mode
    Uint32 CTR_WIDTH    : 2; // 8:7 AES-CTR Mode Counter Width
    Uint32 ICM          : 1; // 9 AES Integer Counter Mode (ICM) Enable
    Uint32 CFB          : 1; // 10 Full block AES cipher feedback mode (CFB128) Enable
    Uint32 XTS          : 2; // 12:11 AES-XTS Operation Enable
    Uint32 F8           : 1; // 13 AES f8 Mode Enable
    Uint32 F9           : 1; // 14 AES f9 Mode Enable
    Uint32 CBCMAC       : 1; // 15 AES-CBC MAC Enable
    Uint32 GCM          : 2; // 17:16 AES-GCM Mode Enable
    Uint32 CCM          : 1; // 18 AES-CCM Mode Enable
    Uint32 CCM_L        : 3; // 21:19 Width of the length field for CCM operations
    Uint32 CCM_M        : 3; // 24:22 Length of the authentication field for CCM operations
    Uint32 rsvd1        : 4; // 28:25 Reserved
    Uint32 SAVE_CONTEXT : 1; // 29 TAG or Result IV Save
    Uint32 SVCTXTRDY    : 1; // 30 AES TAG/IV Block(s) Ready
    Uint32 CTXTRDY      : 1; // 31 Context Data Registers Ready
};

union AES_CTRL_REG
{
    Uint32 all;
    struct AES_CTRL_BITS bit;
};

struct AES_SYSCONFIG_BITS
{                                            // bits description
    Uint32 AUTOIDLE                    : 1;  // 0 autoidle
    Uint32 SOFTRESET                   : 1;  // 1 Soft Reset
    Uint32 SIDLE                       : 2;  // 3:2 Slave Idle Mode
    Uint32 rsvd1                       : 1;  // 4 Reserved
    Uint32 DMA_REQ_DATA_IN_EN          : 1;  // 5 DMA Request Data In Enable
    Uint32 DMA_REQ_DATA_OUT_EN         : 1;  // 6 DMA Request Data Out Enable
    Uint32 DMA_REQ_CONTEXT_IN_EN       : 1;  // 7 DMA Request Context In Enable
    Uint32 DMA_REQ_CONTEXT_OUT_EN      : 1;  // 8 DMA Request Context Out Enable
    Uint32 MAP_CONTEXT_OUT_ON_DATA_OUT : 1;  // 9 Map Context Out on Data Out Enable
    Uint32 rsvd2                       : 1;  // 10 Reserved
    Uint32 rsvd3                       : 1;  // 11 Reserved
    Uint32 rsvd4                       : 1;  // 12 Reserved
    Uint32 rsvd5                       : 3;  // 15:13 Reserved
    Uint32 rsvd6                       : 16; // 31:16 Reserved
};

union AES_SYSCONFIG_REG
{
    Uint32 all;
    struct AES_SYSCONFIG_BITS bit;
};

struct AES_SYSSTATUS_BITS
{                          // bits description
    Uint32 RESETDONE : 1;  // 0 Reset Done
    Uint32 rsvd1     : 15; // 15:1 Reserved
    Uint32 rsvd2     : 16; // 31:16 Reserved
};

union AES_SYSSTATUS_REG
{
    Uint32 all;
    struct AES_SYSSTATUS_BITS bit;
};

struct AES_IRQSTATUS_BITS
{                            // bits description
    Uint32 CONTEXT_IN  : 1;  // 0 Context In Interrupt Status
    Uint32 DATA_IN     : 1;  // 1 Data In Interrupt Status
    Uint32 DATA_OUT    : 1;  // 2 Data Out Interrupt Status
    Uint32 CONTEXT_OUT : 1;  // 3 Context Output Interrupt Status
    Uint32 rsvd1       : 12; // 15:4 Reserved
    Uint32 rsvd2       : 16; // 31:16 Reserved
};

union AES_IRQSTATUS_REG
{
    Uint32 all;
    struct AES_IRQSTATUS_BITS bit;
};

struct AES_IRQENABLE_BITS
{                            // bits description
    Uint32 CONTEXT_IN  : 1;  // 0 Context In Interrupt Enable
    Uint32 DATA_IN     : 1;  // 1 Data In Interrupt Enable
    Uint32 DATA_OUT    : 1;  // 2 Data Out Interrupt Enable
    Uint32 CONTEXT_OUT : 1;  // 3 Context Out Interrupt Enable
    Uint32 rsvd1       : 12; // 15:4 Reserved
    Uint32 rsvd2       : 16; // 31:16 Reserved
};

union AES_IRQENABLE_REG
{
    Uint32 all;
    struct AES_IRQENABLE_BITS bit;
};

struct AES_DIRTY_BITS_BITS
{                         // bits description
    Uint32 S_ACCESS : 1;  // 0 AES Access Bit
    Uint32 S_DIRTY  : 1;  // 1 AES Dirty Bit
    Uint32 rsvd1    : 1;  // 2 Reserved
    Uint32 rsvd2    : 1;  // 3 Reserved
    Uint32 rsvd3    : 12; // 15:4 Reserved
    Uint32 rsvd4    : 16; // 31:16 Reserved
};

union AES_DIRTY_BITS_REG
{
    Uint32 all;
    struct AES_DIRTY_BITS_BITS bit;
};

struct AES_REGS
{
    Uint32 AES_KEY2_6;                       // XTS Second Key or CBC-MAC Third Key
    Uint32 AES_KEY2_7;                       // XTS Second Key or CBC-MAC Third Key
    Uint32 AES_KEY2_4;                       // XTS/CCM Second Key or CBC-MAC Third Key
    Uint32 AES_KEY2_5;                       // XTS Second Key or CBC-MAC Third Key
    Uint32 AES_KEY2_2;                       // XTS/CCM/CBC-MAC Second Key or Hash Key Input
    Uint32 AES_KEY2_3;                       // XTS/CCM/CBC-MAC Second Key or Hash Key Input
    Uint32 AES_KEY2_0;                       // XTS/CCM/CBC-MAC Second Key or Hash Key Input
    Uint32 AES_KEY2_1;                       // XTS/CCM/CBC-MAC Second Key or Hash Key Input
    Uint32 AES_KEY1_6;                       // Key
    Uint32 AES_KEY1_7;                       // Key
    Uint32 AES_KEY1_4;                       // Key
    Uint32 AES_KEY1_5;                       // Key
    Uint32 AES_KEY1_2;                       // Key
    Uint32 AES_KEY1_3;                       // Key
    Uint32 AES_KEY1_0;                       // Key
    Uint32 AES_KEY1_1;                       // Key
    Uint32 AES_IV_IN_OUT_0;                  // Initialization Vector 0
    Uint32 AES_IV_IN_OUT_1;                  // Initialization Vector 1
    Uint32 AES_IV_IN_OUT_2;                  // Initialization Vector 2
    Uint32 AES_IV_IN_OUT_3;                  // Initialization Vector 3
    union AES_CTRL_REG AES_CTRL;             // Input/Output Buffer Control and Mode Selection
    Uint32 AES_C_LENGTH_0;                   // Crypto Data Length 0
    Uint32 AES_C_LENGTH_1;                   // Crypto Data Length 1
    Uint32 AES_AUTH_LENGTH;                  // AAD Data Length
    Uint32 AES_DATA_IN_OUT_0;                // Data Word 0
    Uint32 AES_DATA_IN_OUT_1;                // Data Word 1
    Uint32 AES_DATA_IN_OUT_2;                // Data Word 2
    Uint32 AES_DATA_IN_OUT_3;                // Data Word 3
    Uint32 AES_TAG_OUT_0;                    // Hash Result 0
    Uint32 AES_TAG_OUT_1;                    // Hash Result 1
    Uint32 AES_TAG_OUT_2;                    // Hash Result 2
    Uint32 AES_TAG_OUT_3;                    // Hash Result 3
    Uint32 AES_REV;                          // Module Revision Number
    union AES_SYSCONFIG_REG AES_SYSCONFIG;   // System Configuration
    union AES_SYSSTATUS_REG AES_SYSSTATUS;   // Reset Status
    union AES_IRQSTATUS_REG AES_IRQSTATUS;   // Interrupt Status
    union AES_IRQENABLE_REG AES_IRQENABLE;   // Interrupt Enable
    union AES_DIRTY_BITS_REG AES_DIRTY_BITS; // Accessed / Dirty Bits
};

//---------------------------------------------------------------------------
// AES External References & Function Declarations:
//
extern volatile struct AES_REGS AesRegs;

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

//===========================================================================
// End of file.
//===========================================================================
